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Schematic

Opamp U1A is used as an amplifier. Its gain depends on the DS resistance of JFET T1. The lower this resistance, the larger the gain of U1.

The resistance between T1's Drain and Source depends on VDS and VGS. To keep VDS as small as possible, R1 and R3 will first devide the input voltage by 100. The voltage between Gate and Source is controlled by U2.

U2 amplifies U1A's output signal. To prevent a too strong low-frequency response, the signal is filtered by an HPF consisting of C2 and R7. U2's gain is determined by P1. D1 makes sure that only negative half cyles make it to the Gate, since the JFET can only pinched off by a negative Gate voltage. The negative half cycles are smoothed by C1. Please note that 'the positive' of C1 is connected to ground, because the voltage across it will always be negative!

A small input voltage will result in a small output voltage at U1A and U2. At T1's Gate, there will thus be a small negative voltage. The DS resistance will therefore be low and U1A's gain will be high.

A larger input voltage will cause a more negative voltage at the Gate, resulting in a higher DS resistance, and a lower gain.

So U1A's gain is higher for small input voltages and smaller for large input voltages. And that is exactly what we want.

The minimum DS resistance of the chosen FET is about 150Ω. The maximum gain of U1A is therefore about 100. The maximum DS resistance is infinite, so the minumum gain is unity.

Assume that P1 has been set so that U2's gain is 10. Also assume that T1's pinch-off voltage is -1.5V. If the input voltage is 0V, U1A's gain will be 100, because the Gate voltage is also 0V.

If the input voltage is 200mVtop the output amplitude at U2 will initially be 200mV/100∙100∙10 = 2V. This voltage will charge C1. This will cause the Gate voltage to become more negative, increasing the DS resistance and decreasing the gain of U1A. The output voltage at U2 will therefore decrease as well. C1 will be charged less and less rapidly. Eventually the Gate voltage will give U1A a gain at which the output voltage at U2 equals the Gate voltage.

What will happen if the Gate voltage is almost equal to the pinch-off voltage and the input voltage is increased even more? The FET will never get pinched-off completely, because U1A's gain will then be unity and that will never be enough to maintain the Gate voltage at pinch-off voltage (unless the input voltage is increased to 15Vtop, but this circuit is not meant for that). So the output voltage at U2 will not increase. This means that the output voltage at U1A cannot increase either. At the certain input voltage (depending on the position of P1 and the pinch-off voltage of the FET) the amplitude of the output voltage remains the same! So this circuit can prevent overdriving the next stage.

The circuit around U1B provides some extra gain.

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